Recently, as the capacity of semiconductor memory devices has increased, the density and integration of memory cells has also increased. In such a memory device, the failure of even a few memory cells leads to the failure of the memory device as a whole, thereby resulting in crucially lowered manufacturing yield. In order to overcome this situation, failed memory cells are replaced by redundant memory cells.
The structure of a prior art semiconductor memory device with redundant memory cells will be explained with reference to FIG. 21. The semiconductor memory device comprises, a main memory cell 1, a redundant memory cell 2 having redundant memory cells which will substitute for possibly failed memory cells in the main memory cell 1, a main decoder 3 for driving the memory cell part 1, a redundant decoder 4 for driving the redundant memory cell 2, a control circuit 5 for controlling the main decoder 3 and the redundant decoder 4, and an input terminal 6 for inputting an address signal and control signal.
In this semiconductor memory device, when an memory cell fails, its address data is stored in a non-volatile memory means (not shown) within the control circuit 5. Here the non-volatile memory means includes either a fuse-blowout memory or an electrically programmed and erasable memory (EPROM or EEPROM).
The read and write operations of this semiconductor memory device are conducted in the following manner:
First, a control signal and address data are input to the input terminals 6. When the address data coincides with data stored in the non-volatile memory means within the control circuit 5, a signal from the control circuit 5 puts the main decoder 3 into a disabled state, thereby preventing write or read operations with the main memory cell 1 and allowing write and read with the redundant memory cell 2.
When fuses are employed for the non-volatile memory means, it is a common practice to cut them by laser beam cutting, namely, an apparatus for generating laser light is needed. Using this process, the fuse is separated into two parts by laser beam cutting so that both sides of the fuse are disconnected. In this case, a complicated adjusting procedure is necessary which confirms the address data of a failed memory cell by means of a tester, controls the irradiating position of a laser light according to the address data, and adjusts the output energy of the laser light.
Although it is possible for a manufacturer to store the address data of failed memory cells found at the shipment test into the non-volatile memory means, it is practically impossible for users themselves to write in the address data of failed memory cells occurring during field operation.
On the other hand, when a memory dedicated for read-out only such as EPROM or EEPROM is employed, it may be possible for users to electrically write in the address data of failed memory cells. In this case, however, an additional manufacturing process step for the EEPROM is needed. Furthermore, when employing a commonly used MONOS type EEPROM, write-in speed is slow although read-out speed is fast, and a high write-in voltage is needed.
This type of prior art semiconductor does not provide the important advantage of ability to replace failed memory cells at anytime without using any additional devices.